1. Field of the Invention
The present invention relates to a method of forming an ESD protection device, more particularly, to a method of forming an ESD protection device with low trigger voltage and small junction capacitance, but without adding any extra mask layer into the conventional CMOS process.
2. Description of the Prior Art
The input signals to a MOS IC are fed to the gate electrodes of MOS transistors. If the voltage applied to the gate insulator becomes excessive, the gate oxide will be broken down. The dielectric breakdown strength of SiO.sub.2 is approximately in the range between 1E7 to 2E7 V/cm. According to a MOS device manufactured by means of the deep-submicron technology (such as 0.18 um technology), the gate oxide has a thickness only about 40 .ANG. and thus will not tolerate to a voltage greater than 8V without being broken down. Although the thinner gate oxide is well in excess of the normal operating voltages of 2.5-V or 3.3-V integrated circuits, a much larger voltage (as high as 2000 V) may be impressed upon the inputs to the circuits during either human-operators or mechanical handling operations. When such a high voltage is applied to the pins of an IC package, its discharge (referred to as electrostatic discharge; ESD) can cause serious damage on the gate oxide of the devices. The ESD event may cause sufficient damage to produce immediate destruction of the device, or it may weaken the oxide strength. Therefore, all pins of MOS ICs must be provided with on-chip ESD protection circuits to prevent such voltages from damaging the MOS gates.
Accordingly, before an ESD applies to the interior devices and damages their gate dielectric, the ESD protection devices have to work and bypass the ESD current. Generally, the breakdown voltage of the PN junction is a key parameter to determine the performance of an ESD protection device. The gate dielectric of integrated circuits is getting thinner in the deep-submicron era, so the breakdown voltage of IC's interior devices is getting lower. Accordingly, it is necessary to reduce the PN-junction's breakdown voltage of the ESD protection devices in order to protect the interior devices before their gate dielectrics are damaged. Therefore, it is a fairly important issue for IC industries to reduce the PN-junction's breakdown voltage of the ESD protection devices.
There are two kinds of PN-junction breakdown, i.e. Zener Breakdown and Avalanche Breakdown. Generally, the Zener Breakdown is used for breakdown mechanism of the ESD protection devices. Zener Breakdown occurs when a reversed bias is strong enough so that the electrons in the valence band of the p-type semiconductor approaching the forbidden gap can tunnel through the forbidden region and appear at the same energy in the conduction band of the n-type semiconductor. Since the probability of transmission of an electron through the barrier is a function of the thickness of the barrier, tunneling is only significant in highly doped material in which the fields are high and the depletion region is narrow. According to some prior arts, an extra step of ESD protection ion-implantation is performed to raise the doping concentration. For example, United Microelectronics Corp. in U.S. Pat. No. 5,585,299 disclosed a method of forming an ESD protection devices, in which an extra step of ESD protection ion-implantation with high energy and high dose is performed to raise the doping concentration and deepen the PN junction. The implantation is performed under the situation that there is no dielectric spacer on the sidewall of the MOS transistor, so that the doping profile of the ion implantation envelopes the LDD (Lightly Doped Drain). However, this process not only needs an extra photo mask for photolithography process, but also increases the junction capacitance so that the transmission speed for input signals becomes much slower.
In order to promote the response speed of the ESD protection devices, United Microelectronics Corp. in U.S. Pat. No. 5,559,352 disclosed a method of forming an ESD protection devices, in which an extra step of P.sup.+ ESD protection implantation with high energy and high dose is performed under the source/drain contacts to lower the breakdown voltage. However, this method needs an extra mask layer to identify the region for ESD implantation.